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3.3V 4M x 64/72-Bit 1 BANK SDRAM Module HYS64(72)V4200GCU-8/-10 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module HYS64(72)V8220GCU-8/-10
PC66 & PC100 168 pin unbuffered COB-DIMM Modules
Preliminary Information
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168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules in COB (" hip-on-board" technique for PC main memory applications c ) One bank 4M x 64, 4Mx72 and two bank 8M x 64, 8M x 72 organisation Optimized for byte-write non-parity and ECC applications JEDEC standard Synchronous DRAMs (SDRAM) Fully PC board layout compatible to INTEL' Rev. 1.0 module specification s SDRAM Performance:
-8 PC100 fCK tAC Clock frequency (max.) Clock access time CAS latency = 2 & 3 100 6 -10 PC66 66 8/7 Units MHz ns
* * * * *
*
Supported Latencies at 100 Mhz operation:
CL 3 2 tRCD 2 2 tRP 2 2 tRC 8 7 CLK CLK
* *
Single +3.3V( 0.3V ) power supply Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh Decoupling capacitors mounted on substrate All inputs, outputs are LVTTL compatible Serial Presence Detect with E 2PROM Utilizes 4M x16 SDRAMs in TSOPII-54 packages 4096 refresh cycles every 64 ms 133,35 mm x 25,40 mm x 4,00 mm card size with gold contact pads
* * * * * * *
Semiconductor Group
1
5.98
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
The HYS64(72)V4200 and HYB64(72)V8220 are an industry standard 168-pin 8-byte Dual in-line Memory Module (DIMM) in COB (" hip-on-board) technique which are organised as 4M x 64, 4M x 72 in an one bank and 8M x 64, c 8M x72 in two banks high speed memory arrays designed with 64Mbit Synchronous DRAMs for non-parity and ECC application. The DIMMs use -8 speed sort 4M x 16 SDRAM devices to meet the PC100 requirements and -10 parts for 66 MHz bus speed applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL' module specification. s The DIMMs have a serial presence detect, implemented with a serial E 2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint, with t.d.b. height.
Ordering Information
Type HYS 64V4200GU-8 HYS 72V4200GU-8 HYS 64V8220GU-8 HYS 64V8220GU-8 HYS 64V4200GU-10 HYS 72V4200GU-10 HYS 64V8220GU-10 HYS 64V8220GU-10 Ordering Code PC100-222-620 PC100-222-620 PC100-222-620 PC100-222-620 PC66-222-620 PC66-222-620 PC66-222-620 PC66-222-620 Package Descriptions
100 Mhz 4M x 64 1 bank SDRAM module 100 MHz 4M x 72 1 bank SDRAM module 100 Mhz 8M x 64 2 bank SDRAM module 100 MHz 8M x 72 2 bank SDRAM module 66 Mhz 4M x 64 1 bank SDRAM module 66 MHz 4M x 72 1 bank SDRAM module 66 Mhz 8M x 64 2 bank SDRAM module 66 MHz 8M x 72 2 bank SDRAM module
Module Height 1" 1" 1" 1" 1" 1" 1" 1"
Pin Names
A0-A11 BA0 , BA1 DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0, CKE1 Address Inputs CLK0 - CLK3 (RA0~ RA11 / CA0 ~ CA7, CA10) Bank Select DQMB0 - DQMB7 Data Input/Output CS0 - CS3 Check Bits (x 72 organisation Vcc only) Row Address Strobe Vss Column Address Strobe SCL Read / Write Input SDA Clock Enable N.C. Clock Input Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Pres. Detect No Connection
Address Format:
4M x 64 4M x 72 8M x 64 8M x 72 Part Number HYS64V4200GU HYS72V4200GU HYS64V8220GU HYS72V8220GU Rows 12 12 12 12 Columns 8 8 8 8 Bank Select 2 2 2 2 Refresh 4k 4k 4k 4k Period 64 ms 64 ms 64 ms 64 ms Interval 15,6 s 15,6 s 15,6 s 15,6 s
Semiconductor Group
2
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
Pin Configuration
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC (CB0) NC (CB1) VSS NC NC VCC WE DQMB0 DQMB1 CS0 DU VSS A0 A2 A4 A6 A8 A10 BA1 VCC VCC CLK0 PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol VSS DU CS2 DQMB2 DQMB3 DU VCC NC NC NC (CB2) NC (CB3) VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL VCC PIN # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC (CB4) NC (CB5) VSS NC NC VCC CAS DQMB4 DQMB5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 NC VCC CLK1 NC PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS CKE0 CS3 DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VCC
Note : Pinnames in brackets are for the x72 ECC versions
Semiconductor Group
3
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
CS0 CS DQMB0 DQ(7:0) DQMB1 DQ(15:8) LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 CS LDQM CB(7:0) DQ0-DQ7 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2 CS
Vcc
UDQM DQ8-DQ15 D4
CS2 CS DQMB2 DQ(23:16) DQMB3 DQ(31:24) LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1 E2PROM (256wordx8bit) A0-A11, BA0, BA1 VCC C VSS RAS, CAS, WE CKE0 CLK1,CLK3 D0 - D3, (D4) D0 - D3, (D4) D0 - D3, (D4)
10 pF
CS DQMB6 DQ(55:48) DQMB7 DQ(63:56) LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3
D0 - D3, (D4) D0 - D3, (D4)
SA0 SA1 SA2 SCL
SA0 SA1 SA2 SCL
SDA WP 47k
CLK0 CLK1 CLK2 CLK3
Clock Wiring 4M x 64 4M x 72 2 SDRAM+15pF 3 SDRAM+10pF Termination Termination 2 SDRAM+15pF 2 SDRAM+15pF Termination Termination
notes: 1) all resistors are 10 Ohms 2) D4 is only used in the x72 ECC version 3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous board layout to obtain minimum DQ trance length
Block Diagram for 4M x 64 and 4M x 72 1 bank SDRAM DIMM modules (HYS64V4200GU) Semiconductor Group 4
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
CS0 CS1 CS DQMB0 DQ(7:0) DQMB1 DQ(15:8) LDQM DQ0-DQ7 UDQM CS LDQM DQ0-DQ7 UDQM DQMB4 DQ(39:32) DQMB5 DQ(47:40) LDQM DQ0-DQ7 UDQM CS LDQM DQ0-DQ7 UDQM CS
DQ8-DQ15 DQ8-DQ15 D4 D0 CS LDQM CS LDQM DQ0-DQ7 UDQM
DQ8-DQ15 DQ8-DQ15 D2 D6
Vcc
CB(7:0)
DQ0-DQ7
Vcc
UDQM
DQ8-DQ15 DQ8-DQ15 D9 D8 CS2 CS3 CS DQMB2 DQ(23:16) DQMB3 DQ(31:24) LDQM DQ0-DQ7 UDQM CS LDQM DQ0-DQ7 UDQM DQMB6 DQ(55:48) DQMB7 DQ(63:56) LDQM DQ0-DQ7 UDQM CS LDQM DQ0-DQ7 UDQM CS
DQ8-DQ15 DQ8-DQ15 D5 D1
DQ8-DQ15 DQ8-DQ15 D3 D7 E2PROM (256wordx8bit)
A0-A11, BA0, BA1 VCC C VSS RAS, CAS, WE CKE0
VDD
D0 - D7, (D8,D9) D0 - D7, (D8,D9) D0 - D7, (D8,D9) D0 - D7, (D8,D9) D0 - D3, (D8)
SA0 SA1 SA2 SCL
SA0 SA1 SA2 SCL
SDA WP 47k
Clock Wiring 8M x 64 8M x 72 CLK0 CLK1 CLK2 CLK3 2 SDRAM+15pF 2 SDRAM+15pF 2 SDRAM+15pF 2 SDRAM+15pF 3 SDRAM+10pF 3 SDRAM+10pF 2 SDRAM+15pF 2 SDRAM+15pF
10k CKE1 D4 - D7,(D9)
notes: 1) all resistors are 10 Ohms 2) D8 & D9 are only used in the x72 ECC version 3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous board layout to obtain minimum DQ trance length
Semiconductor Group
5
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VDD,VDDQ = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 2.0 mA) Output low voltage (IOUT = 2.0 mA) Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC) Symbol Limit Values min. max. Vcc+ 0.3 0.8 - 0.4 10 10 V V V V A A 2.0 - 0.5 2.4 - - 10 - 10 Unit
VIH VIL VOH VOL II(L) IO(L)
Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter Symbol Limit Values max. 4M x 72 Input capacitance (A0 to A11, RAS, CAS, WE) Input capacitance (CS0 -CS3, ) Input capacitance (CLK0 - CLK3) Input capacitance (CKE0, CKE1) Input capacitance (DQMB0 - DQMB7) Input / Output capacitance
(DQ0-DQ63,CB0-CB7)
Unit
max. 8M x 72 tbd. tbd. tbd. tbd. tbd. tbd. 8 10 pF pF pF pF pF pF pF pF
CI1 CI2 CICL CI3 CI4 CIO
Csc Csd
tbd. tbd. tbd. tbd. tbd. tbd. 8 10
Input Capacitance (SCL,SA0-2) Input/Output Capacitance
Semiconductor Group
6
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
Standby and Refresh Currents (Ta = 0 to 70 oC, VCC = 3.3V 0.3V)) 1) Parameter & Test Condition
OPERATING CURRENT trc=trcmin., tck=tckmin. Active-precharge command cycling, without burst operation PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) NO OPERATING CURRENT tck = min., CS = VIH(min), active state ( max. 4 banks) tck = min. tck = Infinity tck = min. tck = Infinity CKE>=VI H(min.) CKE<=VIL (max.) (Power down mode) ICC2P ICC2P S ICC2 ICC2S 1 bank operation Symb.
4Mx64 4Mx72 8Mx64 8Mx72 max. 440 550 440 550
Note
ICC1
mA
1
12 8 200 20 280
15 10 250 25 350
12 8 200 20 280
15 10 250 25 350
mA mA mA mA mA
1
1
ICC3
ICC3P
32
40
32
40
mA
BURST OPERATING CURRENT tck = min., Read/Write command cycling AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V
ICC4
620
775
620
775
mA 1, 2 mA
1
ICC5
520
650
520
650
ICC6
8
10
8
10
mA
Semiconductor Group
7
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
AC Characteristics 3)4) TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 1 ns Parameter
Symbol
Limit Values -8 min. -10 max. max. min.
Unit
Note
Clock and Clock Enable
Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System Frequency CAS Latency = 3 CAS Latency = 2 Clock Access Time CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Input Setup time Input Hold Time CKE Setup Time (Power down mode) CKE Setup Time (Self Refresh Exit) Transition time (rise and fall)
tCK
10 10 10 15 100 100 6 6 - - - - - - - - - - - 3 3 2.5 1 2.5 10 1 100 66 7 8 - - - - - - - ns ns MHz MHz ns ns ns ns ns ns ns ns ns
2, 4
fCK
- -
tAC
- -
tCH tCL tCS tCH tCKSP tCKSR tT
3 3 2 1 2 10 1
6 6 7 7 8 9
Common Parameters
RAS to CAS delay Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time CAS to CAS delay time (same bank)
tRCD tRC tRAS tRP tRRD tCCD
20 70 45 20 16 1
- - - - - -
24
90
- - - - - -
ns ns ns ns ns CLK
2 CLK 7 CLK 5 CLK 2 CLK 1 CLK
60 24 20 1
Refresh Cycle
Self Refresh Exit Time Refresh Period (4096 cycles)
tSREX tREF
10 64
- -
ns ms
9) 8)
Semiconductor Group
8
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
Parameter
Symbol
Limit Values -8 min. -10 max. - - 10 max. min. - - 8 - 3 0 3 2
Unit
Note
Read Cycle
Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
tOH tLZ tHZ tDQZ
3 0 3 2
ns ns ns CLK
2, 4
10
Write Cycle
Write Recovery Time DQM Write Mask Latency
tWR tDQW
8 0
- -
10
- -
CLK CLK
0
Semiconductor Group
9
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
Notes: 1. The specified values are valid when addresses are changed no more than once during tck(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ' are stable during tRC(min.). s) 3. All AC characteristics are shown for device level. An initial pause of 100s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V il = 0.4 V and V ih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V ih and Vil. All AC measurements assume t T=1ns with the AC output load circuit show. Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.
tCH 2.4 V CLOCK 0.4 V tCL tSETUP tHOLD
+ 1.4 V 50 Ohm Z=50 Ohm I/O 50 pF
tT
INPUT
1.4V
tAC tLZ tOH
tAC
I/O 50 pF
1.4V
OUTPUT
Measurement conditions for tac and toh
tHZ
5. 6. 7. 8.
fig.1 If clock rising time is longer than 1ns, a time (t T/2 -0.5) ns has to be added to this parameter. Rated at 1.5 V If tT is longen than 1 ns, a time (t T -1) ns has to be added to this parameter. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to " ake-up"the device. w 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10.Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
Semiconductor Group
10
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence detect protocol ( I 2C synchronous 2-wire bus)
SPD-Table for -8 modules:
Byte# Description SPD Entry Value 4Mx64 -8 80 08 04 0C 08 01 40 00 01 A0 60 00 80 10 00 01 8F 04 06 01 01 00 06 A0 60 FF FF 14 10 Hex 4Mx72 -8 80 08 04 0C 08 01 48 00 01 A0 60 02 80 10 08 01 8F 04 06 01 01 00 06 A0 60 FF FF 14 10 8Mx64 -8 80 08 04 0C 08 02 40 00 01 A0 60 00 80 10 00 01 8F 04 06 01 01 00 06 A0 60 FF FF 14 10 8Mx72 -8 80 08 04 0C 08 02 48 00 01 A0 60 02 80 10 08 01 8F 04 06 01 01 00 06 A0 60 FF FF 14 10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for 16 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont' d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General Minimum Clock Cycle Time at CAS Latency =2 Maximum data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD
128 256 SDRAM 12 8 1/2 64 0 LVTTL 10.0 ns 6.0 ns none Self-Refresh, 15.6s x16 n/a / x8 tccd = 1 CLK 1, 2, 4, 8 & full page 4 CL = 2 & 3 CS latency = 0 WL = 0 non buffered/ non reg. Vcc tol +/- 10% 10.0 ns 6.0 ns not supported not supported 20 ns 16 ns
Semiconductor Group
11
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
SPD-Table (cont' ): d
Byte# Description SPD Entry Value 4Mx64 -8 14 2D 08 20 10 20 10 FF 12 D7 XX 64 AF FF Hex 4Mx72 -8 14 2D 08 20 10 20 10 FF 12 E9 XX 64 AF FF 8Mx72 -8 14 2D 08 20 10 20 10 FF 12 D8 XX 64 FF FF 8Mx72 -8 14 2D 08 20 10 20 10 FF 12 EA XX 64 FF FF
29 30 31 32 33 34 35 62-61
Minimum RAS to CAS delay tRCD Minimum RAS pulse width tRAS Module Bank Density (per bank) SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information (optional) 125 (FFh if not used) 126 Max. Frequency Specification 127 100 Mhz support details 128+ Unused storage locations
20 ns 45 ns 32 MByte 2 ns 1 ns 2 ns 1 ns
Revision 1.2
100 MHz
SPD-Table for -10 modules:
Byte# Description SPD Entry Value 4Mx64 -10 80 08 04 0C 08 01 40 00 01 A0 70 00 80 10 00 01 8F Hex 4Mx72 -10 80 08 04 0C 08 01 48 00 01 A0 70 02 80 10 08 01 8F 8Mx64 -10 80 08 04 0C 08 02 40 00 01 A0 70 00 80 10 00 01 8F 8Mx72 -10 80 08 04 0C 08 02 48 00 01 A0 70 02 80 10 08 01 8F
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x16 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont' d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported
128 256 SDRAM 12 8 1/2 64 0 LVTTL 10.0 ns 7.0 ns none Self-Refresh, 15.6s x16 n/a / x8 tccd = 1 CLK 1, 2, 4, 8 & full page
Semiconductor Group
12
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
SPD-Table (cont' ): d
Byte# Description SPD Entry Value 4Mx64 -10 04 06 01 01 00 06 F0 80 FF FF 18 14 18 3C 08 25 10 25 10 FF 12 7C XX 66 AF FF Hex 4Mx72 -10 04 06 01 01 00 06 F0 80 FF FF 18 14 18 3C 08 25 10 25 10 FF 12 8E XX 66 AF FF 8Mx64 -10 04 06 01 01 00 06 F0 80 FF FF 18 14 18 3C 08 25 10 25 10 FF 12 7D XX 66 FF FF 8Mx72 -10 04 06 01 01 00 06 F0 80 FF FF 18 14 18 3C 08 25 10 25 10 FF 12 8F XX 66 FF FF
17 18 19 20 21 22 23
Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes
SDRAM Device Attributes :General Minimum Clock Cycle Time at CAS Latency =2 24 Maximum data access time from Clock for CL=2 25 Minimum Clock Cycle Time at CL = 1 26 Maximum Data Access Time from Clock at CL=1 27 Minimum Row Precharge Time 28 Minimum Row Active to Row Active delay tRRD 29 Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 32-61 Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information (optional) 125 (FFh if not used) 126 Max. Frequency Specification 127 Support details 128+ Unused storage locations
4 CL = 2 & 3 CS latency = 0 WL = 0 non buffered/ non reg. Vcc tol +/- 10% 15.0 ns 8.0 ns not supported not supported 24 ns 20 ns 24 ns 60 ns 32 MByte 2.5 ns 1 ns 2.5 ns 1 ns
Revision 1.2
66 MHz
Semiconductor Group
13
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
SDRAM DIMM COB-Module package
Semiconductor Group
14
HYS64(72)V4200/8220GCU-8/-10 SDRAM-Modules
Semiconductor Group
15

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